NOC:Synthesis of Digital Systems


Lecture 1 - Outline - What is Synthesis?


Lecture 2 - Chip Design Flow and Hardware Modelling


Lecture 3 - VHDL: Introduction to Hardware Description Languages and VHDL Basics


Lecture 4 - VHDL: Modelling Timing - Events and Transactions


Lecture 5 - VHDL: Specifying Hardware Behaviour with Processes


Lecture 6 - VHDL: Specifying Structure, Test Benches, Parameterisation, and Libraries


Lecture 7 - Introduction to High-level Synthesis


Lecture 8 - Language front-end Design Representation


Lecture 9 - Compiler Transformation in High Level Synthesis: Constant Folding, Dead Code Elimination, Constant Propagation, and Strength Reduction


Lecture 10 - Memory Modelling and Compiler Transformation in High Level Synthesis: Common Sub-expression Elimination and Loop Invariant Code Motion


Lecture 11 - Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining


Lecture 12 - Hardware Transformations and ASAP / ALAP Scheduling


Lecture 13 - Scheduling in High Level Synthesis: List Scheduling and Time-constrained Scheduling


Lecture 14 - Force Directed Scheduling and Register Allocation


Lecture 15 - High Level Synthesis and Timing Issues


Lecture 16 - Finite State Machine Synthesis: Introduction to FSM Encoding


Lecture 17 - Finite State Machine Synthesis: Identifying Common Cubes and Graph Embeding


Lecture 18 - The Retiming Problem


Lecture 19 - Efficient Solution to Retiming and Introduction to Logic Synthesis


Lecture 20 - Binary Decision Diagrams


Lecture 21 - Introduction to Logic Synthesis


Lecture 22 - Two-level Logic Optimisation


Lecture 23 - Multi-Level Logic Optimisation


Lecture 24 - Multi-level Logic Synthesis: Technology Mapping


Lecture 25 - Introduction to Timing Analysis


Lecture 26 - Timing Analysis and Critical Paths