NOC:Embedded Systems-Design Verification and Test


Lecture 1 - Introduction


Lecture 2 - Modeling Techniques - 1


Lecture 3 - Modeling Techniques - 2


Lecture 4 - Hardware/Software Partitioning - 1


Lecture 5 - Hardware/Software Partitioning - 2


Lecture 6 - Introduction to Hardware Design


Lecture 7 - Hardware Architectural Synthesis - 1


Lecture 8 - Hardware Architectural Synthesis - 2


Lecture 9 - Hardware Architectural Synthesis - 3


Lecture 10 - Hardware Architectural Synthesis - 4


Lecture 11 - Hardware Architectural Synthesis - 5


Lecture 12 - Hardware Architectural Synthesis - 6


Lecture 13 - Hardware Architectural Synthesis - 7


Lecture 14 - System Level Analysis


Lecture 15 - Uniprocessor Scheduling - 1


Lecture 16 - Uniprocessor Scheduling - 2


Lecture 17 - Multiprocessor Scheduling - 1


Lecture 18 - Multiprocessor Scheduling - 2


Lecture 19 - Introduction and Basic Operators of Temporal Logic


Lecture 20 - Syntax and Semantics of CTL


Lecture 21 - Equivalence between CTL formulas


Lecture 22 - Model Checking Algorithm


Lecture 23 - Binary Decision Diagram


Lecture 24 - Use of OBDDs for State Transition System


Lecture 25 - Symbolic Model Checking


Lecture 26 - Introduction to Digital VLSI Testing


Lecture 27 - Automatic Test Pattern Generation (ATPG)


Lecture 28 - Scan Chain based Sequential Circuit Testing


Lecture 29 - Software-Hardware Co-validation Fault Models and High Level Testing for Complex Embedded Systems


Lecture 30 - Testing for embedded cores


Lecture 31 - Bus and Memory Testing


Lecture 32 - Testing for advanced faults in Real time Embedded Systems


Lecture 33 - BIST for Embedded Systems


Lecture 34 - Concurrent Testing for Fault tolerant Embedded Systems - 1


Lecture 35 - Concurrent Testing for Fault tolerant Embedded Systems - 2


Lecture 36 - Testing for Re-programmable hardware


Lecture 37 - Interaction Testing between Hardware and Software