NOC:Digital IC Design


Lecture 1 - Introduction - Digital IC Design


Lecture 2 - PN Junction


Lecture 3 - MOS Capacitor Threshold Voltage


Lecture 4 - MOS Transistor Current Expression


Lecture 5 - Body Effect and I-V Plots


Lecture 6 - Short Channel Transistors - Channel Length Modulation


Lecture 7 - Velocity Saturation and Level-1 SPICE Model


Lecture 8 - Drain Induced Barrier Lowering


Lecture 9 - Sub-Threshold Leakage


Lecture 10 - Substrate and Gate Leakage


Lecture 11 - The PMOS Transistor


Lecture 12 - Transistor Capacitance


Lecture 13 - Transistor Capacitance


Lecture 14 - CMOS Inverter Construction


Lecture 15 - Voltage Transfer Characteristics


Lecture 16 - Load Line Analysis


Lecture 17 - Trip Point for Short Channel Device Inverter


Lecture 18 - Trip Point for Long Channel Device Inverter


Lecture 19 - Noise Margin Analysis - 1


Lecture 20 - Noise Margin Analysis - 2


Lecture 21 - Noise Margin Analysis - 3


Lecture 22 - Noise Margin Analysis-Long Channel Device Inverter - 1


Lecture 23 - Noise Margin Analysis-Long Channel Device Inverter - 2


Lecture 24 - Pass Transistors


Lecture 25 - NMOS Transistor ON Resistance and Fall Delay


Lecture 26 - Elmore Delay Model


Lecture 27 - Inverter: Transient Response


Lecture 28 - Inverter: Dynmaic Power


Lecture 29 - Inverter: Short Circuit Power


Lecture 30 - Inverter: Leakage Power and Transistor Stacks


Lecture 31 - Stacking Effect and Sleep Transistors


Lecture 32 - Ring Oscillators and Process Variations


Lecture 33 - Implementing Any Boolean Logic Function


Lecture 34 - Implementing Any Boolean Logic Function: Examples. Gate sizing


Lecture 35 - Gate Sizing


Lecture 36 - Logic Gate Capacitance


Lecture 37 - Gate Delay


Lecture 38 - Parasitic Delay


Lecture 39 - Gate Delay with a Load Capacitance


Lecture 40 - Logical Effort


Lecture 41 - Gate Delay


Lecture 42 - Path Delay Calculation and Optimization Formulation


Lecture 43 - Buffer Insertion


Lecture 44 - Input Ordering and Asymmetric Gates


Lecture 45 - Skewed Gates


Lecture 46 - Special Functions


Lecture 47 - Pseudo NMOS Logic


Lecture 48 - Pseudo NMOS Inverter


Lecture 49 - Pseudo NMOS Logical Effort and CVSL


Lecture 50 - Dynamic Circuits and Input Monotonicity


Lecture 51 - Domino Logic and Weak Keepers


Lecture 52 - Transmission Gate Logic


Lecture 53 - Gate Sizing for Large Circuits


Lecture 54 - Ripple Adder Introduction


Lecture 55 - Full Adder Circuit Implementation


Lecture 56 - Full Adder Optimization


Lecture 57 - Carry Skip Adder


Lecture 58 - Carry Select Adder


Lecture 59 - Linear and Square Root Carry Select Adder


Lecture 60 - Two's Complement Arithmetic


Lecture 61 - Two's Complement Sign Extension


Lecture 62 - Array Multiplier


Lecture 63 - Array Multiplier - Timing Analysis


Lecture 64 - Carry Save Multiplier


Lecture 65 - Carry Save Multiplier - Signed Multiplication


Lecture 66 - Introduction to Pipelining


Lecture 67 - Time Borrowing


Lecture 68 - Master Slave Flip Flop


Lecture 69 - Flop Timing Parameters


Lecture 70 - Alternate Circuit Implementations


Lecture 71 - Clock Overlap


Lecture 72 - C2MOS Flop


Lecture 73 - Flop Characterization


Lecture 74 - Max and Min Delay of Flop Based Systems


Lecture 75 - Flop Min Delay Constraint


Lecture 76 - Latch-Max and Min Delay Constraints


Lecture 77 - Latch-Timing Analysis with Skew


Lecture 78 - Time Borrowing